Multiple finger metal-oxide-semiconductor field effect transistor (MOSFET) structures are conventionally used in high frequency applications because the reduced resistances of multiple finger MOSFETs give rise to improved high frequency performance compared to single gate MOSFET transistors. In addition, for the short channel lengths and large gate widths of modem MOSFETs, a single gate would be extensive in one dimension, posing a layout problem. This problem is alleviated in a multi-finger layout because the gate width is distributed among the fingers.
However, the trend in integrated circuit (IC) design involves the increase in device performance and functionality with a decrease in device size and fabrication complexity. Multiple finger MOS devices having gate lengths below 5 nm is an emerging technology. However, the fabrication of such devices is typically complex, requiring multiple masking and etching steps, even for devices having symmetric active regions. For multiple finger MOS devices having asymmetric active areas, the fabrication techniques are even more complex.
Accordingly, it is desirable to provide a method for fabricating multiple finger MOS transistors that reduces the number of masking and etching steps used. In addition, it is desirable to provide a method for fabricating multiple finger MOS transistors that uses spacer lithography to achieve small device dimensions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.